A typical example of the read only memory device is illustrated in FIG. 1 of the drawings and comprises a memory cell array 1 having a plurality of memory cells arranged in rows and columns, and the memory cells in the respective rows are accompanied by bit lines 2, respectively. Each of the memory cells provides or does not provide a conduction path between one of the bit lines 2 and the ground depending upon a data bit preserved therein when the memory cell is accessed. The bit lines 2 are grouped by four, and these four bit lines have gate transistors 3, 4, 5 and 6, respectively. In order to specify the memory cells each selected from each of the rows, the read only memory device further comprises a first decoder circuit 7, and a second decoder circuit 8. The first decoder circuit 7 and second decoder circuit 8 are supplied from a control circuit, or an internal address generator 9 with eight bits of an internal address signal and two bits of the internal address signal, respectively, and the internal address signal is produced on the basis of the data bits read out from the memory cells during the previous read-out operation. The first decoder circuit 7 has a plurality of control lines each coupled to the gate electrodes of the memory cells in each column, and the second decoder circuit 8 has four control lines each coupled to every fourth gate transistor. Namely, the first control line of the second decoder circuit 8 is coupled to the gate transistors each provided in the first bit line of each bit line group, and the second control line of the second decoder circuit 8 is coupled to the gate transistors each provided in the second bit line of each bit line group. Similarly, the third control line of the second decoder circuit 8 is coupled to the gate transistors each provided in the third bit line of each bit line group, and the fourth control line of the second decoder circuit 8 is coupled to the gate transistors each provided in the fourth bit line of each bit line group. All of the bit line groups are coupled to input nodes of a plurality of buffer circuits 10, 11 and 12, respectively, and output nodes of the buffer circuits 10, 11 and 12 are coupled to input nodes of a plurality of flip-flop circuits 13, 14 and 15, respectively. The flip-flop circuits 13, 14 and 15 are triggered by a clock pulse CL and respectively latch the data bits appearing at the respective output node of the buffer circuits 10, 11 and 12. Output nodes of the flip-flop circuits 13, 14 and 15 are coupled in parallel to data input nodes of the control circuit 9 as well as a destination. All of the bit lines 2 are supplied with a positive voltage level through precharging transistors one of which is shown and designated by reference numeral 16.
The read-out operation will be hereinunder described in detail with reference to FIG. 2 of the drawings. Assuming now that data bits accessed in the previous read-out operation are latched by the flip-flop circuits 13, 14 and 15 in synchronous with a clock pulse CL at time t1, the data bits are supplied from the flip-flop circuits 13, 14 and 15 to the control circuit 9 and the destination at time t2, then the control circuit 9 latches the data bits fed from the flip-flop circuits 13, 14 and 15. The control circuits 9 carries out an operation to produce a new internal address signal, and the eight bits of the new internal address signal are supplied from the control circuit 9 to the first decoder circuit 7 at time t3. With the eight bits of the new internal address signal, the first decoder circuit 7 allows one of the control lines thereof to go up to an active high level at time t4, so that memory cells in one of the columns turn on or remain in the off states depending upon the data bits preserved therein. As described hereinbefore, all of the bit lines 2 are supplied with the positive voltage level, and, for this reason, the bit lines have either high or ground voltage level depending upon the state of the memory cells. Thus, each data bit of either high or ground voltage level appears on each of the bit lines 2. The two bits of the internal address signal have been supplied from the control circuit 9 to the second decoder circuit 8, so that the second decoder circuit 8 allows one of the control lines thereof, for example the first control line, to go up to an active high level at time t4. When the first control line goes up to the active high level, the gate transistors including the gate transistor 3 turn on to transfer the data bits to the buffer circuits 10, 11 and 12, thereby causing the buffer circuits 10, 11 and 12 to latch the data bits at time t5. When the clock pulse CL appears at the flip-flop circuits 13, 14 and 15, the data bits are latched by the flip-flop circuits 13, 14 and 15, respectively, at time t6, and the data bits are transferred from the flip-flop circuits 13, 14 and 15 to the control circuit 9 and the destination as similar to the data bits read out during the previous read-out operation at time t7. With the data bits, the control circuit 9 produces a new internal address which is fed to the first and second decoder circuits 7 and 8, and, thus, the read only memory repeats the read-out operations.
However, a problem is encountered in the prior-art read only memory device in that a long time period is required for every single read-out operation. Namely, a first time period T1 measuring from t1 to t3 is needed for propagation of the data bits from the latching operation of the flip-flop circuits 13, 14 and 15 to production of the new internal address signal, and a second time period T2 measuring from time t3 to time t6 is consumed for the decoding of the new internal address signal, the read-out of the new data bits and transferring the new data bits to the flip-flop circuits 13, 14 and 15. Thus, the first time period T1 is followed by the second time period T2, so that every single read-out operation needs a long time period T3 which is approximately equal to the sum of the first and second time periods T1 and T2. This results in a low operation speed for a read-out operation.